Network processors are dedicated processors that act as programmable packet forwarding engines for network routers. Since these processors have to interact with the packet buffers for packet forwarding or routing, the design of network processors is typically closely tied to the design of the overall routing system. Normally packet buffer management is closely related to the system architecture and is designed to suit the packet buffer size, packet queuing algorithms, and buffer allocation and deallocation techniques employed, as well as any other specific issues relating to packet processing.
To achieve contemporary wire speed packet processing and efficient usage of available memory resources, an effective technique for managing packet buffers in networking environments and buffer management scalable to the varying needs of system requirements are both essential.
There is, therefore, a need in the art for a system independent and scalable packet buffer management architecture for network processors.